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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. general description the max5130/max5131 are low-power, 13-bit, voltage- output digital-to-analog converters (dacs) with an inter- nal precision bandgap reference and output amplifier. the max5130 operates on a single +5v supply with an internal reference of +2.5v, and is capable of a +4.0955v full-scale output. if necessary, the user can override the on-chip, <10ppm/? voltage reference with an external reference. the max5131, operating on +3v, delivers its +2.04775v full-scale output with an internal precision ref- erence of +1.25v. both devices draw only 500? of sup- ply current, which reduces to 3a in power-down mode. in addition, their power-up reset feature allows for a user- selectable initial output state of either 0v or midscale and minimizes output voltage glitches during power-up. the serial interface is compatible with spi, qspi, and microwire, which makes the max5130/max5131 suitable for cascading multiple devices. each dac has a double-buffered input organized as an input register fol- lowed by a dac register. a 16-bit shift register loads data into the input register. the dac register may be updated independently or simultaneously with the input register. both devices are available in a 16-pin qsop package and are specified for the extended-industrial (-40? to +85?) temperature range. for pin-compatible 14-bit upgrades, see the max5170/max5172 data sheet; for pin-compatible 12-bit versions, see the max5120/ max5121 data sheet. applications industrial process control automatic test equipment (ate) digital offset and gain adjustment motion control ?-controlled systems features ? single-supply operation +5v (max5130) +3v (max5131) ? full-scale output range +4.0955v (max5130) +2.04775v (max5131) ? built-in 10ppm/? (max) precision bandgap reference +2.5v (max5130) +1.25v (max5131) ? adjustable output offset ? spi/qspi/microwire-compatible, 3-wire serial interface ? pin-programmable shutdown mode and power- up reset (0v or midscale output voltage) ? buffered output capable of driving 5k || 100pf or 4?0ma loads ? space-saving 16-pin qsop package ? pin-compatible upgrades to the 12-bit max5120/max5121 ? pin-compatible 14-bit upgrades available (max5170/max5172) max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 os v dd refadj ref agnd pd upo dout dgnd top view max5130 max5131 qsop out rstval cs pdl clr din sclk 19-1429; rev 0; 2/99 pin configuration ordering information spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. part max5130 aeee max5130beee inl (lsb) ?.5 -40? to +85? -40? to +85? temp. range pin- package 16 qsop 16 qsop ? max5131 aeee max5131beee ? -40? to +85? -40? to +85? 16 qsop 16 qsop ?
max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics?ax5130 (+5v) (v dd = +5v ?0%, os = agnd = dgnd = 0v, 33nf capacitor at refadj, internal reference, r l = 5k , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd, dgnd ...............................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v digital inputs to dgnd.............................................-0.3v to +6v digital outputs (dout, upo) to dgnd .....-0.3v to (v dd + 0.3v) out to agnd.............................................-0.3v to (v dd + 0.3v) os to agnd ...................................(agnd - 4v) to (v dd + 0.3v) ref, refadj to agnd ..............................-0.3v to (v dd + 0.3v) maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) qsop (derate 8.00mw/? above +70?) .....................667mw operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10sec) .............................+300? v in = 0 or v dd max5130a refadj = v dd 4.5v v dd 5.5v max5130b max5130b max5130a max5130a code = 1fff hex, t a = +25? t a = +25? conditions pf 8 c in input capacitance ? -1 0.001 1 i in input leakage current mv 200 v hys input hysteresis v 0.8 v il input low voltage v 3 v ih input high voltage ? 3.3 7 refadj current ppm/? 24 tcv ref 16 output voltage temperature coefficient v 2.5 v ref output voltage -0.5 0.5 bits 13 n resolution ?/v 20 250 psrr power-supply rejection ratio ppm/? 10 50 tcv fs 330 full-scale temperature coefficient (note 3) v 4.0463 4.0955 4.1447 v fs full-scale voltage lsb -1 1 dnl differential nonlinearity mv -10 10 v os offset error (note 2) -3 -0.2 3 mv ge gain error units min typ max symbol parameter i sink = 2ma i source = 2ma v 0.13 0.4 v ol output low voltage v v dd - 0.5 v oh output high voltage max5130b lsb -1 1 inl integral nonlinearity (note 1) 0 i out 100? (sourcing) ?/? 0.1 1 v out /i out reference external load regulation ma 4 reference short-circuit current static performance reference digital input digital outputs
max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference _______________________________________________________________________________________ 3 electrical characteristics?ax5130 (+5v) (continued) (v dd = +5v ?0%, os = agnd = dgnd = 0v, 33nf capacitor at refadj, internal reference, r l = 5k , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) to ?.5lsb, v step = 4v cs = v dd , f sclk = 100khz, v sclk = 5vp-p conditions ? 320 i shdn power-supply current in shutdown ? 500 600 i dd power-supply current (note 5) v 4.5 5.5 v dd power-supply voltage (note 5) nv-s 5 digital feedthrough ms 2 time required to exit shutdown k 83 121 r os os input resistance ? 20 output settling time v 0 to v dd output voltage swing (note 4) units min typ max symbol parameter electrical characteristics?ax5131 (+3v) (v dd = +3v ?0%, os = agnd = dgnd = 0v, 33nf capacitor at refadj, internal reference, r l = 5k , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) max5131a refadj = v dd 2.7v v dd 3.3v max5131b max5131b max5131a max5131a data = 1fff hex, t a = +25? t a = +25? conditions mv 200 v hys input hysteresis v 0.8 v il input low voltage v 2.2 v ih input high voltage ? 3.3 7 refadj current ma 4 reference short-circuit current ppm/? 10 tcv ref max5131b 3 0 i out 100? (sourcing) output voltage temperature coefficient v 1.25 v ref output voltage -1 1 ?/? 0.1 1 bits 13 n resolution ?/v 20 250 psrr power-supply rejection ratio ppm/? 10 30 tcv fs lsb 310 v out /i out full-scale temperature coefficient (note 3) v 2.02317 2.04775 2.07232 v fs full-scale voltage lsb -1 1 dnl differential nonlinearity mv -10 10 v os offset error (note 2) -5 -0.2 5 reference external load regulation mv ge gain error units min typ max symbol parameter -2 2 inl integral nonlinearity (note 1) v/? 0.6 sr voltage output slew rate dynamic performance power requirements static performance reference digital input r l =
max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference 4 _______________________________________________________________________________________ electrical characteristics?ax5131 (+3v) (continued) (v dd = +3v ?0%, os = agnd = dgnd = 0v, 33nf capacitor at refadj, internal reference, r l = 5k , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) to ?.5lsb, v step = 2v cs = v dd , f sclk = 100khz, v sclk = 3vp-p conditions ? 320 i shdn power-supply current in shutdown ? 500 60 i dd power-supply current (note 5) v 2.7 3.6 v dd power-supply voltage (note 5) nv-s 5 digital feedthrough ms 2 time required to exit shutdown k 83 121 r os os input resistance ? 20 output settling time v 0 to v dd output voltage swing (note 4) units min typ max symbol parameter i sink = 2ma v 0.13 0.4 v ol output low voltage i source = 2ma v v dd - 0.5 v oh output high voltage v in = 0 or v dd ? -1 0.001 1 i in input leakage current pf 8 c in input capacitance v/? 0.6 sr voltage output slew rate timing characteristics?ax5130 (+5v) (v dd = +5v ?0%, os = agnd = dgnd = 0v, 33nf capacitor at refadj, internal reference, r l = 5k , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) ns 40 t css cs fall to sclk rise setup time ns 40 t cl sclk pulse width low conditions ns 100 t cp sclk clock period ns 40 t ch sclk pulse width high ns 0 t csh sclk rise to cs rise hold time ns 10 t cs0 sclk rise to cs fall delay time ns 40 t ds sdi setup time ns 0 t dh sdi hold time units min typ max symbol parameter ns 100 t csw cs pulse width high ns 40 t cs1 cs rise to sclk rise hold time c load = 200pf ns 80 t do1 sclk rise to dout valid propagation delay time c load = 200pf ns 80 t do2 sclk fall to dout valid propagation delay time digital outputs power requirements dynamic performance
max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference _______________________________________________________________________________________ 5 note 1: accuracy is guaranteed as shown in the following table: note 2: offset is measured at the code closest to 10mv. note 3: the temperature coefficient is determined by the ?ox?method in which the maximum d v out over the temperature range is divided by d t. note 4: accuracy is better than 1.0lsb for v out = 10mv to (v dd - 180mv). guaranteed by psr test on end points. note 5: r load = and digital inputs are at either v dd or dgnd. timing characteristics?ax5131 (+3v) (v dd = +3v ?0%, os = agnd = dgnd = 0v, 33nf capacitor at refadj, internal reference, r l = 5k , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) ns 60 t css cs fall to sclk rise setup time ns 150 ns c load = 200pf 75 t csw t cl sclk pulse width low conditions ns 150 t cp sclk clock period ns 75 t ch sclk pulse width high ns 0 t csh sclk rise to cs rise hold time cs pulse width high ns 75 t cs1 cs rise to sclk rise hold time c load = 200pf ns 200 t do1 sclk rise to dout valid propagation delay time ns 200 t do2 sclk fall to dout valid propagation delay time ns 10 t cs0 sclk rise to cs fall delay time ns 60 t ds sdi setup time ns 0 t dh sdi hold time units min typ max symbol parameter 20 5 40 3 8191 8191 accuracy guaranteed to code: from code: v dd (v) typical operating characteristics (v dd = +5v (max5130), v dd = +3v (max5131), r l = 5k , c l = 100pf, os = agnd, t a = +25?, unless otherwise noted.) -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0 2000 4000 6000 8000 10,000 max5130 integral nonlinearity vs. digital input code max5130/31 toc01 digital input code inl (lsb) -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0 2000 4000 6000 8000 10,000 max5130 differential nonlinearity vs. digital input code max5130/31 toc02 digital input code dnl (lsb) 2.490 2.495 2.500 2.505 2.510 -60 -20 20 60 -40 0 40 80 100 max5130 reference voltage vs. temperature max5130/31 toc03 temperature (?) reference voltage (v)
max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = +5v (max5130), v dd = +3v (max5131), r l = 5k , c l = 100pf, os = agnd, t a = +25?, unless otherwise noted.) 200 250 300 350 400 450 500 -60 -20 -40 0 20406080100 max5130 supply current vs. temperature max5130/31 toc04 temperature (?) supply current ( m a) (code = 1555 hex) (code = 0000 hex) 250 300 400 350 450 500 4.0 4.5 5.0 5.5 (code = 1555 hex) (code = 0000 hex) 6.0 max5130 supply current vs. supply voltage max5130/31 toc05 supply voltage (v) supply current ( m a) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -60 -20 -40 0 20406080100 max5130 shutdown current vs. temperature max5130/31 toc06 temperature (?) shutdown current ( m a) 4.093 4.094 4.095 4.096 4.097 4.098 4.099 -60 -20 -40 0 20406080100 max5130 full-scale output vs. temperature max5130/31 toc07 temperature (?) full-scale output (v) r l = 5k w c l = 100pf cs 5v/div out 1v/div 5 m v/div max5130 dynamic response fall time max5130/31-10 0.1 1 10 100 max5130 full-scale error vs. resistive load max5130/31 toc08 resistor (k w ) full-scale error (lsb) 0.5 -3.0 -2.0 -2.5 -1.5 -1.0 -0.5 0 cs 5v/div out 1v/div 5 m s/div max5130 dynamic response rise time max5130/31-09 sclk 2v/div out 1mv/div ac coupled 2 m s/div max5130 digital feedthrough (sclk, out) max5130/31-11 cs 2v/div out 100mv/div ac coupled 5 m s/div max5130 major carry transition max5130/31-12
max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference _______________________________________________________________________________________ 7 -0.3 -0.1 -0.2 0.1 0 0.2 0.3 0 4000 2000 6000 8000 10,000 max5131 integral nonlinearity vs. digital input code max5130/31 toc-13 digital input code inl (lsb) -0.25 -0.15 0.05 -0.05 0.15 0.25 4000 2000 6000 8000 10,000 max5131 differential nonlinearity vs. digital input code max5130/31 toc-14 digital input code dnl (lsb) 0 1.240 1.242 1.246 1.244 1.248 1.250 -60 -20 0 -40 20 40 60 80 100 max5131 reference voltage vs. temperature max5130/31 toc-15 temperature (?) reference voltage (v) 100 150 300 250 200 350 400 -60 -20 0 -40 20 40 60 80 100 max5131 supply current vs. temperature max5130/31 toc-16 temperature (?) supply current ( m a) code = 1555 hex code = 0000 hex 2.036 2.038 2.042 2.040 2.044 2.046 -60 -20 0 -40 20 40 60 80 100 max5131 full-scale output vs. temperature max5130/31 toc-19 temperature (?) full-scale output (v) r l = 5k w c l = 100pf 250 300 275 350 325 375 400 2.5 2.9 3.1 2.7 3.3 3.5 3.7 max5131 supply current vs. supply voltage max5130/31 toc-17 supply voltage (v) supply current ( m a) code = 1555 hex code = 0000 hex 0 0.2 0.6 0.4 0.8 1.0 -60 -20 0 -40 20 40 60 80 100 max5131 shutdown current vs. temperature max5130/31 toc-18 temperature (?) shutdown current ( m a) 0.5 -1.5 0.1 10 100 max5131 full-scale output vs. resistive load 0 -0.5 -1.0 max5130/31 toc-20 resistor (k w ) full-scale error (lsb) 1 cs 2v/div out 500mv/div 2 m s/div max5131 dynamic response rise time max5130/31-21 typical operating characteristics (continued) (v dd = +5v (max5130), v dd = +3v (max5131), r l = 5k , c l = 100pf, os = agnd, t a = +25?, unless otherwise noted.)
max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = +5v (max5130), v dd = +3v (max5131), r l = 5k , c l = 100pf, os = agnd, t a = +25?, unless otherwise noted.) cs 2v/div out 500mv/div 2 m s/div max5131 dynamic response fall time max5130/31-22 sclk 2v/div out 500 m v/div ac coupled 2 m s/div max5131 digital feedthrough (sclk, out) max5130/31-23 cs 2v/div out 100mv/div ac coupled 5 m s/div max5131 major carry transition max5130/31-24 pin description pin offset adjust (analog input) os 1 function name analog output voltage. high impedance if part is in shutdown. out 2 power-down lockout (digital input) 1: normal operation. 0: disallows shutdown (device cannot be powered down). pdl 4 reset value input (digital input) 1: tie to v dd to select midscale as the output reset value. 0: tie to dgnd to select 0v as the output reset value. rstval 3 active-low chip-select input (digital input) cs 6 serial clock input sclk 8 serial data input. data is clocked in on the rising edge of sclk. din 7 reset dac input (digital input). clears the dac to its predetermined (rstval) output state. clearing the dac will cause it to exit a software shutdown state. clr 5 serial data output dout 10 power-down input (digital input). pulling pd high when pdl = v dd places the ic into shutdown with a maximum shutdown current of 20?. pd 12 user-programmable output (digital output) upo 11 buffered reference output/input. in internal reference mode, the reference buffer provides a +2.5v (max5130) or +1.25v (max5131) nominal output, externally adjustable at refadj. in external reference mode, disable the internal reference by pulling refadj to v dd and applying the external reference to ref. ref 14 positive power supply. bypass with a 0.1? capacitor in parallel with a 4.7? capacitor to agnd. v dd 16 analog reference adjust input. bypass with a 33nf capacitor to agnd. connect to v dd when using an external reference. refadj 15 analog ground agnd 13 digital ground dgnd 9
max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference _______________________________________________________________________________________ 9 _______________detailed description the max5130/max5131 13-bit, voltage-output dacs are easily configured with a 3-wire serial interface. they include a 16-bit data-in/data-out shift register and have a double-buffered input consisting of an input register and a dac register. in addition, these devices employ precision bandgap references and trimmed internal resistors to produce a gain of 1.6384v/v, maximizing the output voltage swing (figure 1). the max5130/ max5131 output amplifier? offset-adjust pin allows for a dc shift in the dac outputs. the full-scale output volt- age is +4.0955v for the max5130 and +2.04775v for the max5131. these dacs are designed with an invert- ed r-2r ladder network (figure 2) that produces a weighted output voltage proportional to the digital input code. internal reference both the max5130 and max5131 use an on-board pre- cision bandgap reference to generate an output volt- age of +2.5v (max5130) or +1.25v (max5131). with a low temperature coefficient of only 10ppm/? (max), the ref pin can source up to 100? and may become unstable with capacitive loads exceeding 100pf. refadj can be used for minor adjustments (1%) to the max5130 max5131 sr control 16-bit shift register decode control input register bandgap reference reference buffer dac register dac 2x (1x) dout upo out os r 0.6384r gain = 1.6384x 4k 1.25v agnd dgnd v dd din sclk cs 2.5v, (1.25v) logic output clr pdl pd rstval refadj ref 13 ( ) for max5131 only figure 1. simplified functional block diagram out os r 0.6384r shown for all 1s on dac *internal 2.5v (max5130) and 1.25v (max5131) or external reference. d0 d10 d11 d12 2r 2r 2r 2r 2r rrr ref* agnd figure 2. simplified inverted r-2r dac structure
max5130/max5131 reference voltage. use the circuits shown in figure 3a (max5130) and figure 3b (max5131) to achieve these adjustments. connect a 33nf capacitor from refadj to agnd to establish low-noise operation of the dac. larger capacitor values may be used, but will result in increased start-up delay. the time constant ( t) for the start-up delay is determined by the refadj input impedance of 4k and c refadj : t = 4k c refadj external reference an external reference may be applied to the ref pin. disable the internal reference by pulling refadj to v dd . this allows an external reference signal (ac- or dc-based) to be fed into the ref pin. for proper oper- ation, do not exceed the input voltage range limits of 0v to (v dd - 1.4v) for v ref . determine the output voltage using the following equa- tion (refadj = v dd ; os = agnd): v out = [v ref (nb / 8192)] 1.6384v/v where nb is the numeric value of the max5130/ max5131 input code (0 to 8191), v ref is the external reference voltage, and 1.6384v/v is the gain of the internal output amplifier. the ref pin has a minimum input resistance of 40k and is code-dependent. output amplifier the output amplifier of the max5130/max5131 employs a trimmed resistor-divider to set a gain of +1.6384v/v and minimize the gain error. with its on- board laser-trimmed +1.25v reference and the output buffer gain, the max5131 achieves a full-scale output of +2.04775v, while the max5130 provides a +4.0955v full-scale output with a +2.5v reference. the output amplifier has a typical slew rate of 0.6v/? and settles to ?.5lsb within 20?, with a load of 5k in parallel with 100pf. loads less than 1k may result in degraded performance. the os pin may be used to adjust the output offset volt- age. for instance, to achieve a +1v offset, apply -1.566v (offset = -[output buffer gain - 1] v os ) to os to produce an output voltage range from +1v to (1v + v ref 1.6384v/v). note that the dac? output range is still limited by the maximum output voltage specification. power-down mode the max5130/max5131 feature software- and hard- ware-programmable (pd pin) shutdown modes that reduce the typical supply current to 3?. to enter soft- ware shutdown mode, program the control sequence for the dac as shown in table 1. in shutdown mode, the amplifier output becomes high- impedance and the serial interface remains active. data in the input registers is saved, allowing the max5130/max5131 to recall the output state prior to entering shutdown when returning to normal operation mode. to exit shutdown mode, load both input and dac registers simultaneously or update the dac regis- ter from the input register. when returning from shut- down mode, wait 2ms for the reference to settle. when using an external reference, the dac requires only 20? for the output to stabilize. +3v/+5v, 13-bit, serial voltage-output dacs with internal reference 10 ______________________________________________________________________________________ refadj +3v 15k 100k 400k 33nf max5131 refadj +5v 90k 100k 400k 33nf max5130 figure 3a. max5130 reference adjust circuit figure 3b. max5131 reference adjust circuit
power-down lockout input ( pdl ) the power-down lockout pin ( pdl ) disables shutdown when low. when in shutdown mode, a high-to-low tran- sition on pdl will wake up the dac with its output still set to the state prior to power-down. pdl can also be used to wake up the device asynchronously. power-down input (pd) pulling pd high places the max5130/max5131 in shut- down mode. pulling pd low will not return the max5130/ max5131 to normal operation. a high-to-low transition on pdl or appropriate commands (table 1) via the ser- ial interface are required to exit power-down. serial-interface configuration (spi/qspi/microwire/pic16/pic17) the max5130/max5131 3-wire serial interface is com- patible with spi, qspi, pic16/pic17 (figure 4) and microwire (figure 5) interface standards. the 2-byte- long serial input word contains three control bits and 13 data bits in msb-first format (table 2). the max5130/max5131? digital inputs are double buffered, which allows the user to: load the input register without updating the dac register, update the dac register with data from the input register, update the input and dac registers concurrently. max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference ______________________________________________________________________________________ 11 load input register; dac register unchanged. 13-bit dac data 0 0 0 1 0 update dac register from input register; exit shutdown. xxxxxxxxxxxxx 0 1 1 1 0 simultaneously load input and dac registers; exit shutdown. 13-bit dac data 0 upo goes low (default). xxxxxxxxxxxxx 1 0 0 0 1 mode 1; dout clocked out on sclk? rising edge. 1xxxxxxxxxxxx 1 1 1 1 0 upo goes high. xxxxxxxxxxxxx 1 no operation. xxxxxxxxxxxxx 0 16-bit serial word shutdown dac (provided pdl = 1). xxxxxxxxxxxxx 1 mode 0; dout clocked out on sclk? falling edge (default). 00xxxxxxxxxxx 1 1 1 c1 c0 c2 function d12 ............... d0 table 1. serial-interface programming commands x = don? care din sclk cs mosi sck i/o spi/qspi port (pic16/pic17) ss v dd cpol = 0, cpha = 0 (che = 1, ckp = 0, smp = 0, sspm3?spm0 = 0001) ( ): pic16/pic17 only max5130 max5131 figure 4. spi/qspi interface connections (pic16/pic17) din sclk cs sk so i/o microwire port max5130 max5131 figure 5. microwire interface connections
max5130/max5131 the 16-bit input word may be sent in two 1-byte pack- ets (spi-, microwire- and pic16/pic17-compatible), with cs low during this period. the control bits c2, c1, and c0 (table 1) determine: the clock edge on which dout is to be clocked out via the serial interface, the state of the user-programmable logic output, the configuration of the device after shutdown. the general timing diagram in figure 6 illustrates how data is acquired. cs must be low for the part to receive data. with cs low, data at din is clocked into the regis- ter on the rising edge of sclk. when cs transitions high, data is latched into the input and/or dac registers, depending on the setting of the three control bits c2, c1, and c0. the maximum serial clock frequency guar- anteed for proper operation is 10mhz for the max5130 and 6.6mhz for the max5131. figure 7 depicts a more detailed timing diagram of the serial interface. table 2. serial data format pic16 with ssp module and pic17 interface the max5130/max5131 are compatible with a pic16/pic17 microcontroller (?), using the synchro- nous serial port (ssp) module. to establish spi com- munication, connect the controller as shown in figure 4 and configure the pic16/pic17 as system master by initializing its synchronous serial port control register (sspcon) and synchronous serial port status register (sspstat) to the bit patterns shown in tables 3 and 4. in spi mode, the pic16/pic17 ?s allow 8 bits of data to be transmitted synchronously and received simulta- neously. two consecutive 8-bit writings (figure 6) are necessary to feed the dac with three control bits and 13 data bits. din data transitions on the serial clock? falling edge and is clocked into the dac on sclk? ris- ing edge. the first 8 bits on din contain the three con- trol bits (c2, c1, and c0) and the first five data bits (d12?8). the second 8-bit word contains the remain- ing bits (d7?0). +3v/+5v, 13-bit, serial voltage-output dacs with internal reference 12 ______________________________________________________________________________________ control bits msb ..... data bits ..... lsb msb ............................................................................... lsb 16 bits of serial data t d12................................d0 c2, c1, c0 cs sclk din command executed 9 8 16 1 c1 c2 d0 c0 d12 d11 d10 d9 d6 d5 d4 d3 d2 d1 d8 d7 figure 6. serial-interface timing sclk din dout t cs0 t css t cl t ch t cp t csw t cs1 t csh t ds t do1 t do2 t dh cs figure 7. detailed serial-interface timing
serial data output the contents of the internal shift register are output serially on dout, allowing for daisy-chaining (see applications information ) of multiple devices as well as data readback. the max5130/max5131 may be pro- grammed to shift data out on dout on the serial clock? rising edge (mode 1) or falling edge (mode 0). the latter is the default during power-up and provides a lag of 16 clock cycles, maintaining spi, qspi, microwire, and pic16/pic17 compatibility. in mode 1, the output data lags din by 15.5 clock cycles. during power-down, dout retains its last digital state prior to shutdown. user-programmable output (upo) the upo feature allows an external device to be con- trolled through the serial-interface setup (table 1), thereby reducing the number of microcontroller i/o ports required. during power-down, this output will retain the last digital state before shutdown. with clr pulled low, upo will reset to the default state after wake-up. max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference ______________________________________________________________________________________ 13 table 3. detailed sspcon register contents receive overflow detection bit x sspov bit6 bit7 clock polarity select bit. ckp = 0 for spi master-mode selection. 0 ckp bit4 bit5 synchronous serial port enable bit 0: disables serial port and configures these pins as i/o port pins. 1: enables serial port and configures sck, sdo and sci as serial-port pins. 1 sspen 0 sspm2 bit2 bit3 1 sspm0 bit0 bit1 control bit 0 sspm1 write collision detection bit x wcol synchronous serial-port control register (sspcon) max5130/max5131 setting synchronous serial port mode select bit. sets spi master mode and selects f clk = f osc / 16. 0 sspm3 x = don? care table 4. detailed sspstat register contents x = don? care spi clock edge select bit. data will be transmitted on the rising edge of the serial clock. 1 cke bit6 buffer full status bit bit7 update address read/write bit information stop bit x p bit4 bit5 data address bit x d/a x r/w bit2 bit3 x bf bit0 bit1 control bit x ua spi data input sample phase. input data is sampled at the mid- dle of the data output time. 0 smp synchronous serial-port control register (sspstat) max5130/max5131 settings start bit x s
max5130/max5131 __________applications information definitions integral nonlinearity (inl) integral nonlinearity (figure 8a) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nulli- fied. for a dac, the deviations are measured at every single step. differential nonlinearity (dnl) differential nonlinearity (figure 8b) is the difference between an actual step height and the ideal value of 1lsb. if the magnitude of the dnl is less than 1lsb, the dac guarantees no missing codes and is monotonic. offset error the offset error (figure 8c) is the difference between the ideal and the actual offset point. for a dac, the off- set point is the step value when the digital input is zero. this error affects all codes by the same amount and can usually be compensated for by trimming. gain error gain error (figure 8d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corre- sponds to the same percentage error in each step. +3v/+5v, 13-bit, serial voltage-output dacs with internal reference 14 ______________________________________________________________________________________ 0 2 1 4 3 7 6 5 000 010 001 011 100 101 110 at step 011 (1/2 lsb ) at step 001 (1/4 lsb ) 111 digital input code analog output value (lsb) figure 8a. integral nonlinearity figure 8c. offset error 0 2 1 3 000 010 001 011 actual diagram ideal diagram actual offset point offset error (+1 1/4 lsb) ideal offset point digital input code analog output value (lsb) 0 2 1 4 3 6 5 000 010 001 011 100 101 differential linearity error (-1/4 lsb) differential linearity error (+1/4 lsb) 1 lsb 1 lsb digital input code analog output value (lsb) figure 8b. differential nonlinearity figure 8d. gain error 0 5 4 6 7 000 101 100 110 111 ideal diagram gain error (-1 1/4 lsb) ideal full-scale output actual full-scale output digital input code analog output value (lsb)
settling time the settling time is the amount of time required from the start of a transition until the dac output settles to its new output value within the converter? specified accuracy. digital feedthrough digital feedthrough is noise generated on the dac? output when any digital input transitions. proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the dac itself. unipolar output figure 9 shows the max5130/max5131 setup for unipolar, rail-to-rail operation with a gain of 1.6384v/v. with its +2.5v internal reference, the max5130 can generate a unipolar output range of 0 to +4.0955v. the max5131 produces a range of 0 to +2.04775v with its on-board +1.25v reference. table 5 lists example codes for unipolar output voltages. an off- set to the output voltage can be achieved by simply connecting the appropriate voltage to the os pin, as shown in figure 10. bipolar output the max5130/max5131 can be configured for unity- gain bipolar operation (os = out) using the circuit shown in figure 11. the output voltage v out is thereby given by the following equation: v out = v ref [ {g (nb / 8192)} - 1] where nb is the numeric value of the dac? binary input code, v ref is the voltage of the internal (or exter- nal) precision reference, and g is the overall gain. the application circuit in figure 11 uses a low-cost opera- tional amplifier (max4162) external to the max5130/ max5131 in a unity-gain configuration. this provides an overall circuit gain of 2v/v. table 6 lists example codes for bipolar output voltages. reset (rstval) and clear ( clr ) functions the max5130/max5131 dacs offer a clear pin ( clr ), which resets the output to a certain value, depending upon how rstval is set. rstval = dgnd sets the output to 0, and rstval = v dd sets the output to mid- scale when clr is pulled low. the clr pin has a minimum input resistance of 40k in series with a diode to the supply voltage (v dd ). if the digital voltage is higher than the supply voltage for the part, a small input current may flow, but this current will be limited to (v clr - v dd - 0.5v) / 40k . note: clearing the dac will also cause the part to exit software shutdown (pd = 0). max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference ______________________________________________________________________________________ 15 max5130 max5131 dac gain = 1.638v/v ref out os dgnd agnd +5v/+3v v dd r 0.6384r figure 9. unipolar output circuit (os = agnd) using internal (+1.25v/+2.5v) or external reference. with external reference, pull refadj to v dd . max5130 max5131 dac agnd dgnd ref refadj out os v os +5v/+3v + v dd r 0.6384r figure 10. circuit for adding offset to the dac? output agnd dgnd r max5130 max5131 dac ref os out 50k 50k v- v+ v dd v out +5v/+3v 0.6384r max4162 figure 11. unity-gain bipolar output circuit using internal (+1.25v/+2.5v) or external reference. with external reference, pull refadj to v dd . rail-to-rail is a registered trademark of nippon motorola, ltd.
max5130/max5131 daisy-chaining devices any number of max5130/max5131s can be daisy- chained simply by connecting the serial data output pin (dout) of one device to the digital input pin (din) of the following device in the chain (figure 12). another configuration allows several max5130/ max5131 dacs to share one common din signal line (figure 13). in this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. however, more i/o lines are required in this configuration, because each ic needs a dedicated cs line. +3v/+5v, 13-bit, serial voltage-output dacs with internal reference 16 ______________________________________________________________________________________ +v ref (4097 / 8192) 1.6384 1 0000 0000 0001 +2.0485v +4.0955v +1.02425v +2.04775v +v ref (4095 / 8192) 1.6384 0 1111 1111 1111 +2.0475v +2.0480v +1.02375v +1.02400v +v ref (4096 / 8192) 1.6384 1 0000 0000 0000 0v 0 0000 0000 0000 0v +0.5mv 0v +0.25mv +v ref (8191 / 8192) 1.6384 1 1111 1111 1111 analog output +v ref (1 / 8192) 1.6384 0 0000 0000 0001 internal reference dac contents msb lsb max5130 max5131 external reference v ref [ {2 (4097 / 8192)} - 1] 1 0000 0000 0001 +610.35? +2.49939v +305.18? +1.24969v dac contents msb lsb v ref [ {2 (4095 / 8192)} - 1] 0 1111 1111 1111 -610.35? 0v -305.18? 0v max5130 v ref [ {2 (4096 / 8192)} - 1] 1 0000 0000 0000 max5130 -v ref 0 0000 0000 0000 -2.5v -2.49939v -1.25v -1.24969v external reference v ref [ {2 (8191 / 8192)} - 1] 1 1111 1111 1111 analog output v ref [ {2 (1 / 8192)} - 1] 0 0000 0000 0001 internal reference table 5. unipolar code table (gain = +1.6384v/v) table 6. bipolar code table for figure 11 to other serial devices max5130 max5131 din sclk cs max5130 max5131 max5130 max5131 din dout dout dout sclk cs i ii iii din sclk cs figure 12. daisy-chaining multiple devices with the digital i/os din/dout
max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference ______________________________________________________________________________________ 17 to other serial devices max5130 max5131 din sclk cs max5130 max5131 din sclk cs max5130 max5131 din i ii iii sclk cs din sclk cs1 cs2 cs3 figure 13. multiple devices share one common digital input (din) dac out max5130 max5131 10k 26k os ref r 0.6384r v dd dgnd agnd +5v/+3v ac reference input 500mvp-p max495 +5v/+3v figure 14. external reference with ac components using an external reference with ac components the max5130/max5131 have multiplying capabilities within the reference input voltage range specifications. figure 14 shows a technique for applying a sinusoidal input to ref, where the ac signal is offset before being applied to the reference input. power-supply and bypassing considerations on power-up, the input and dac registers are cleared to either zero (rstval = dgnd) or midscale (rstval = v dd ). bypass the power supply with a 4.7? capaci- tor in parallel with a 0.1? capacitor to agnd. minimize lead lengths to reduce lead inductance. layout considerations digital and ac transient signals coupling to agnd can create noise at the output. connect agnd to the high- est quality ground available. use proper grounding techniques, such as a multilayer board with a low- inductance ground plane. wire-wrapped boards and sockets are not recommended. if noise becomes an issue, shielding may be required.
max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference 18 ______________________________________________________________________________________ package information ___________________chip information transistor count: 3308 substrate connected to agnd qsop.eps
max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference ______________________________________________________________________________________ 19 notes
max5130/max5131 +3v/+5v, 13-bit, serial voltage-output dacs with internal reference maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1999 maxim integrated products printed usa is a registered trademark of maxim integrated products. notes

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